The present invention relates to a voltage level shifter circuit for shifting a voltage of an input signal to a higher voltage and a nonvolatile semiconductor storage device using the circuit.
Conventionally, there has been ETOX (EPROM THIN OXIDE: Trademark of Intel Corporation) as a flash memory (whole erase type memory) used most generally. FIG. 5 shows a schematic sectional view of the flash memory cell of this ETOX type. In FIG. 5, a floating gate 5 is formed on a substrate (well) 3 between a source 1 and a drain 2 via a tunnel oxide film 4. Furthermore, a control gate 7 is formed on the floating gate 5 via a layer insulation film 6.
The operational principle of the ETOX type flash memory will be described next. Table 1 shows an example of application voltages in the modes of write, erase and read.
As shown in Table 1 , a voltage Vpp of 10 V is applied to the control gate 7 in the case of write, a reference voltage Vss of 0 V is applied to the source 1, and a voltage Vpgd of 6 V is applied to the drain 2. By the above operation, a large current (500 xcexcA per cell) flows through a channel layer. In the above stage, channel hot electrons are generated in a channel portion of a high electric field on the side of the drain 2. As a consequence, the electrons are injected from the channel portion into the floating gate 5, causing an increase in a threshold voltage. Thus, there is executed write into the memory cell in which write should be done. In the column of the drain 2 in Table 1, 0 V written side by side with 6 V is an application voltage to the drain 2 of the memory cell that is not subjected to write.
In the case of erase, a voltage Vnn of xe2x88x929 V is applied to the control gate 7, a voltage Vpe of 6 V is applied to the source 1, and the drain 2 is made open. The erase of the memory cell is thus executed with the threshold voltage reduced by extracting electrons to the source 1.
In the case of read of the memory cell that has been written (programmed) or erased as described above, there are applied a voltage of 3 V to the control gate 7, a voltage of 1 V to the drain 2 and a voltage of 0 V to the source 1. When data stored in the memory cell is in a written state, no cell current flows and thus it is judged that the stored data is xe2x80x9c0xe2x80x9d. This is because the threshold voltage of the memory cell is not lower than 3.5 V. When data of the memory cell is in an erased state, the threshold voltage is not higher than 2.0 V, and therefore a cell current flows and it is judged that the stored data is xe2x80x9c1xe2x80x9d. It is to be noted that the above-mentioned judgment is executed by sensing a current that flows from the drain 2 to the source 1 by means of a sense circuit (not shown) provided on the side of the drain 2.
For devices that use a voltage different from a voltage of an input signal during write, erase and read, there is EPROM (Erasable and Programmable Read Only Memory) such as an ultraviolet erasable type EPROM besides the above-stated flash memory. In these devices, the voltage applied to each node is varied during write, erase and read, as described above. Moreover, a voltage higher than Vcc (power voltage) is necessary during write and read. Therefore, the voltage of the input signal is required to be shifted to a higher voltage in the device. A circuit used in this case is called a level shifter circuit. The aforementioned power voltage Vcc takes the value of 1.8 V, 3 V or 5 V for example. In contrast to this, the value of 8 V, 10 V or 12 V is taken as a high voltage.
Conventionally, as the aforementioned level shifter circuit, there has been a high voltage level shifter circuit as disclosed in Japanese Patent Laid-Open Publication No. HEI 6-236694. Operation of the high voltage level shifter circuit will be described below with reference to FIG. 6. In FIG. 6, the voltage of Vpp e.g. 12 V is applied as a voltage hvpp. In this state, when a power voltage Vcc e.g. 1.8 V is inputted as an input signal xe2x80x9cinxe2x80x9d, then a transistor Tr3 is turned on and a transistor Tr4, to which the input signal xe2x80x9cinxe2x80x9d is inputted via an inverter INV1, is turned off. By the above operation, a transistor Tr2 is turned on, and a transistor Tr1 is turned off. As a result, a voltage at a level of Vpp e.g. 12 V is outputted as an output signal xe2x80x9coutxe2x80x9d.
On the other hand, when the reference voltage Vss e.g. 0 V is applied as the input signal xe2x80x9cinxe2x80x9d, the transistor Tr3 is turned off, while the transistor Tr4 is turned on. By the above operation, the transistor Tr2 is turned off, and the transistor Tr1 is turned on. As a result, a voltage at a level of Vpp e.g. 12 V is outputted as an output signal xe2x80x9coutbxe2x80x9d, and a voltage at Vss level is outputted as the output signal xe2x80x9coutxe2x80x9d.
Therefore, in the aforementioned high voltage level shifter circuit, the level of the input signal xe2x80x9cinxe2x80x9d is shifted from (Vccxe2x88x92Vss) to (Vppxe2x88x92Vss). In this case, the output signal xe2x80x9coutbxe2x80x9d is a signal obtained by inverting the level of the output signal xe2x80x9coutxe2x80x9d.
However, the high voltage level shifter circuit shown in FIG. 6 has the following problems. That is, considered is the case where the level of the input signal makes the transition from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d in a state in which the voltage hvpp is Vpp e.g. 12 V and the level of the output signal xe2x80x9coutxe2x80x9d is xe2x80x9cHxe2x80x9d (i.e., Vpp e.g. 12 V). In this case, the drain voltage of an n-MOS (Metal-Oxide Semiconductor) transistor Tr4 prior to the transition of the level of the input signal xe2x80x9cinxe2x80x9d is Vpp, while a gate voltage and a source voltage are each Vss e.g. 0 V. If the level of the input signal xe2x80x9cinxe2x80x9d makes a transition, then the gate of the n-MOS transistor Tr4 changes from 0 V to 1.8 V. Consequently, there momentarily exists a state in which the transistor Tr4 is turned on and the gate voltage is lower than the drain voltage. This corresponds to, for example, a state in which the drain voltage is between 1.8 V and 12 V and the gate voltage is 1.8 V. In the above-mentioned state, a large amount of hot carriers are generated in a channel region between the source and the drain, and hot holes move toward the gate, consequently trapping the holes in the gate insulator of the transistor Tr4. If the above-mentioned operation is repeated, then the leak characteristic of the transistor Tr4 in the OFF state is deteriorated. In this case, the n-MOS transistor Tr3, which is operating in a similar manner, is similarly deteriorated.
In the case of the flash memory, since the above-described write and erase operations are executed, the state in which holes are trapped in the gate insulator of the transistors will be repeated tens of thousands of times. Consequently, increased OFF-leak occurs in the high voltage level shifter circuit as shown in FIG. 6, and this incurs a current increase in a standby state in which the device is not operating.
Accordingly, it is considered to insert a cascade transistor for voltage alleviation use as disclosed in Japanese Patent Laid-Open Publication No. HEI 6-236694 as a means for solving the aforementioned problem. FIG. 7 shows a circuit diagram of the high voltage level shifter circuit of the above type. As is apparent from FIG. 7, a cascade n-MOS transistor Tr9 is interposed between a transistor Tr5 and a transistor Tr7, while a cascade n-MOS transistor Tr10 is interposed between a transistor Tr6 and a transistor Tr8. A power voltage Vcc e.g. 1.8 V is applied to the gates of the cascade transistor Tr9 and the cascade transistor Tr10. The operation of the high voltage level shifter circuit having the aforementioned circuit construction will be described below.
Before the level of the input signal xe2x80x9cinxe2x80x9d is transited from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, a voltage of 12 V is applied to a drain of the cascade transistor Tr10, a voltage of 1.8 V is applied to a gate of Tr10, and a source voltage of Tr10 is 1.8 Vxe2x88x92Vthn (Vthn: threshold voltage of n-MOS transistor). On the other hand, a drain voltage of the transistor Tr8 is 1.8 Vxe2x88x92Vthn, a gate voltage of Tr8 is 0 V, and a source voltage of Tr8 is 0 V.
When the level of the input signal xe2x80x9cinxe2x80x9d starts to transit from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, the transistor Tr8 is turned on, and the source voltage of the cascade transistor Tr10 becomes 0 V since the transistor Tr8 is turned on. Hot carriers are generated also in the cascade transistor Tr10 similarly to the operation of the transistor Tr4 shown in FIG. 6 as described above, and hot holes are trapped in the gate insulator of the cascade transistor Tr10. Consequently, the OFF-leak characteristic of the cascade transistor Tr10 is deteriorated. The same thing can be said for the cascade transistor Tr9. However, the transistor Tr8 is not deteriorated because the transistor Tr8 has a drain voltage of 1.8 Vxe2x88x92Vthn, a gate voltage of 1.8 V and a source voltage of 0 V even under the worst conditions. Therefore, in the case of the high voltage level shifter circuit shown in FIG. 7, the characteristics of the cascade transistors Tr9 and Tr10 are deteriorated whereas neither the transistor Tr7 nor Tr8 is deteriorated. As a result, the disadvantageous current increase in the standby state does not occur differently from the case of a high voltage level shifter circuit that has no cascade transistor as shown in FIG. 6.
However, the general high voltage level shifter circuit as shown in FIGS. 6 and 7 has another problem as follows, and the size of the transistor is required to be optimized. This matter will be described below.
First of all, it is considered, for example, the case where the voltage Vpp of 12 V is applied to hvpp and the power voltage Vcc of 1.8 V is applied to the input signal xe2x80x9cinxe2x80x9d in the high voltage level shifter circuit shown in FIG. 6. In this case, the n-MOS transistors Tr3 and Tr4 are turned on by the gate voltage of 1.8 V. On the other hand, the p-MOS transistors Tr1 and Tr2 are turned on by the gate voltage of 0 V. Then, the drains, sources and channel regions of the p-MOS transistors Tr1 and Tr2 exist in an n-well, and this n-well is connected to the voltage Vpp of 12 V. Therefore, the voltage Vpp of 12 V is applied to the backgate of the p-MOS transistors Tr1 and Tr2, and the p-MOS transistors Tr1 and Tr2 are turned on by a potential difference of 12 V, meaning that the p-MOS transistors Tr1 and Tr2 have very high abilities to flow a current.
Therefore, when the operation of the high voltage level shifter circuit is optimized by adjusting the inversion level, it is required to match the abilities of the n-MOS transistors Tr3 and Tr4 with the abilities of the p-MOS transistors Tr1 and Tr2. That is, for example, the channel width of the n-MOS transistors Tr3 and Tr4 is required to be about three times the channel width (about six times in ability) of the p-MOS transistors Tr1 and Tr2.
As described above, the requirement for increasing the n-MOS transistor for the matching of the ability of the n-MOS transistor with the ability of the p-MOS transistor becomes more significant when the reduction in voltage is promoted with the provision of a cascade transistor as shown in FIG. 7.
As is apparent from FIG. 7, when the cascade transistors Tr9 and Tr10 are interposed, the circuit ability of pulling in to, in particular, the reference voltage Vss of the output signal xe2x80x9coutxe2x80x9d is reduced when considered as a level shifter circuit. Therefore, it is required to improve the abilities of the n-MOS transistors Tr7 and Tr8 in order to stably operate the level shifter circuit. In this case, the channel width of the n-MOS transistors Tr7 and Tr8 is doubled as compared with the case where neither the cascade transistor Tr9 nor Tr10 is interposed, and it is further desirable to make the cascade transistors Tr9 and Tr10 have an equivalent size.
FIG. 8 shows one example of waveforms of the input signal xe2x80x9cinxe2x80x9d and the output signals xe2x80x9coutxe2x80x9d and xe2x80x9coutbxe2x80x9d in the high voltage level shifter circuit that is increased in size and provided with cascades. As is apparent from FIG. 8, by comparison with waveforms (FIG. 9) of the input signal xe2x80x9cinxe2x80x9d and the output signals xe2x80x9coutxe2x80x9d and xe2x80x9coutbxe2x80x9d in the high voltage level shifter circuit provided with no cascade transistor, the inversion level is located near a voltage of 6 V (=Vpp (12 V)/2) although time required for inversion becomes slightly long, meaning that the operation is optimized.
In the case of the high voltage level shifter circuit that includes cascades but is not increased in size, waveforms of the input signal xe2x80x9cinxe2x80x9d and the output signals xe2x80x9coutxe2x80x9d and xe2x80x9coutbxe2x80x9d are shown in FIG. 10, where the inversion level is increased to a voltage of 8 V. Therefore, if no optimization is effected in the high voltage operation, then there occurs a trouble that the inverting operation is not performed in the worst case. Therefore, it is required to increase the channel width W of the transistors Tr7 and Tr8.
The following will describe in what circuit construction the aforementioned level shifter circuit is employed for the flash memory. FIG. 11 shows one example of the flash memory circuit construction. In FIG. 11, there are high voltage level shifter circuits HV00 through HV02 that constitute the output stage of a column decoder and have the construction shown in FIG. 7.
In FIG. 11, all the memory cells M are arranged in a matrix form and constitute a block. Drains of memory cells M00, M01, M02, . . . arranged in the direction of column are connected commonly to a bit line B0. Drains of memory cells M10, M11, M12, . . . are connected commonly to a bit line B1, and similar connections are provided for other memory cells. Control gates of the memory cells M00, M10, . . . arranged in the direction of row are connected commonly to a word line W0. Control gates of the memory cells M01, M11, . . . arranged in the direction of row are connected commonly to a word line W1, and similar connections are provided for the other memory cells. Furthermore, the sources of all the memory cells M are connected commonly to a source line S.
During write (programming), a voltage Vpp (12 V, for example) is applied to a power source hvpp, and an input signal xe2x80x9cinxe2x80x9d at the Vcc level is inputted to a high voltage level shifter circuit HV00. As a result, an output signal at the power source hvpp level is outputted from the high voltage level shifter circuit HV00. The transistor Tr00 is thus turned on.
Subsequently, the input signal xe2x80x9cinxe2x80x9d at the Vcc level is first inputted to a high voltage level shifter circuit HV01 so as to select the bit line B0, and an output signal at the power source hvpp level is outputted. As a result, the transistor Tr01 is turned on, and the voltage of the power source hvpp is applied to the bit line B0. On the other hand, the input signal xe2x80x9cinxe2x80x9d at the Vss level is inputted to high voltage level shifter circuits HV02, . . . , and an output signal at the Vss level is outputted. As a result, transistors Tr11, . . . are put in the OFF state.
In the meantime, the voltage Vpp e.g. 12 V is applied to the word lines so as to first select the word line W0. The word line WO and the bit line B0 are thus selected to select the memory cell M00. The voltage Vpp (12 V) is applied to the control gate of the memory cell M00, and the power source hvpp (=Vpp of 12 V) is applied to the drain. If a voltage e.g. 0 V is applied to the source line S, then the threshold voltage is increased to execute write.
The bit line B and the word line W are sequentially selected in a similar manner to execute write in a specified memory cell M.
Next, the operation during read will be described next. During read, a voltage Vcc (1.8 V, for example) is applied to the power source hvpp, and the input signal xe2x80x9cinxe2x80x9d at the reference voltage Vss (0 V, for example) is inputted to the high voltage level shifter circuit HV00 inside the program circuit. As a result, an output signal at the Vss level is outputted from the high voltage level shifter circuit HV00. The transistor Tr00 is thus turned off. In this case, a voltage of 1 V is separately applied to a sense node SN although it is not described in detail.
Subsequently, the input signal xe2x80x9cinxe2x80x9d at the Vcc level is inputted to the high voltage level shifter circuit HV01 similarly to the case of write, and the transistor Tr01 is turned on to apply the voltage of 1 V of the sense node SN to the bit line B0. On the other hand, the input signal xe2x80x9cinxe2x80x9d at the Vss level is inputted to the high voltage level shifter circuits HV02, . . . , and the transistors Tr11, . . . are turned off. The bit line B0 is thus selected. Further, a voltage of 3 V is applied to the word line W0 to select the word line W0 and the memory cell M00.
If the memory cell M00 is in the write state (program state) in the above case, then the threshold voltage of the memory cell M00 is not lower than 3.5 V. Therefore, the memory cell M00 is not turned on even if a voltage of 3 V is applied to the word line W0, and no cell current flows. If the memory cell M00 is not in the program state, then the threshold voltage of the memory cell M00 is not higher than 2.0 V. Therefore, the memory cell M00 is turned on by the application of a voltage of 3 V to the word line W0, and a cell current flows from the drain of the memory cell M00 to the source line S.
This cell current is sensed as a change in voltage at the sense node SN by a sense amplifier SA. In this case, by appropriately determining the value of a reference voltage Ref in the sense amplifier SA, it can be determined whether or not the voltage of the sense node SN has reduced from 1 V. Therefore, it is determined whether or not the memory cell M00 is in the write state (not reduced from 1 V) or in the erase state (reduced from 1 V) by the sense amplifier SA, and the output signal xe2x80x9coutxe2x80x9d, which represents the result of determination, is outputted.
Next, the output stage of a row decoder for applying a voltage corresponding to each operation of the word lines W0, W1, W2, . . . will be described. As described above, the voltage Vpp (12 V) higher than the power voltage Vcc (1.8 V) is applied to the selected word line W during write. Also during read, a voltage of 3 V higher than the power voltage Vcc (1.8 V) is applied. Therefore, the high voltage level shifter circuits HV10, V11, V12, . . . are employed also for the output stage of the row decoder.
FIG. 12 shows a circuit diagram of a high voltage level shifter circuit employed in the output stage of the row decoder. This high voltage level shifter circuit outputs an output signal xe2x80x9coutbxe2x80x9d which is a signal obtained by inverting the input signal xe2x80x9cinxe2x80x9d. When the input signal. xe2x80x9cinxe2x80x9d has xe2x80x9cHxe2x80x9d level (Vcc, for example), an output signal xe2x80x9coutbxe2x80x9d is outputted at Vss of xe2x80x9cLxe2x80x9d level. When the input signal xe2x80x9cinxe2x80x9d has xe2x80x9cLxe2x80x9d level (Vss), an output signal xe2x80x9coutbxe2x80x9d is outputted at hvpp of xe2x80x9cHxe2x80x9d level.
As shown in FIG. 12, a high voltage blocking transistor Tr11 is provided in the input stage of the high voltage level shifter circuit, and this allows a voltage not lower than Vcc to be inputted as the signal in of xe2x80x9cHxe2x80x9d level.
First of all, it is assumed that, during write that is in the high voltage operation, the voltage Vpp (12 V, for example) is applied to the power source hvpp and a power voltage Vcc is 1.8 V. The voltage Vcc is applied to the gate of a cascade n-MOS transistor Tr12. If the input signal xe2x80x9cinxe2x80x9d at xe2x80x9cLxe2x80x9d level (reference voltage Vss e.g. 0 V) is inputted in this state, then the n-MOS transistor Tr13 is turned off. Since the high voltage blocking n-MOS transistor Tr11 has been turned on, the potential of the node A becomes Vss, and thereby the p-MOS transistor Tr14 is turned on. Therefore, the output signal xe2x80x9coutbxe2x80x9d rises, and the voltage hvpp (12 V) is outputted. As a result, the p-MOS transistor Tr15 is put in the OFF state, and the level of the node A is fixed to Vss. Consequently, the output signal xe2x80x9coutbxe2x80x9d (voltage hvpp) is stably outputted at xe2x80x9cHxe2x80x9d level.
Next, when the input signal xe2x80x9cinxe2x80x9d at xe2x80x9cHxe2x80x9d level (Vcc of 1.8 V) is inputted, the transistor Tr13 is turned on and the cascade transistor Tr12 remains in the ON state. On the other hand, the potential of the node A first becomes 1.8 Vxe2x88x92Vthn (Vthn: threshold voltage of n-MOS transistor) via the high voltage blocking transistor Tr11. By this operation, the ability of the p-MOS transistor Tr14 is reduced, and the output signal xe2x80x9coutbxe2x80x9d is pulled in to the Vss level. Consequently, the p-MOS transistor Tr15 is turned on, and the potential of the node A is pulled up to the voltage hvpp. As a result, the p-MOS transistor Tr14 is completely turned off, and the voltage of the output signal xe2x80x9coutbxe2x80x9d is fixed to Vss and stabilized.
In this case, the reason why the cascade transistor Tr12 is interposed is to alleviate the stress applied to the transistor Tr13 similarly to the case of the high voltage level shifters HV01, HV02, . . . for the column decoder. Moreover, in order to secure the operation margin of the cascade transistor Tr12 and the transistor Tr13 similarly to the case of the high voltage level shifters HV01, HV02, . . . , it is required to improve the ability to flow a current at the ON time by increasing, for example, the channel width.
Next, during read in the low voltage operation, a voltage Vrc (3 V, for example) is applied to the power source hvpp. Then, similarly to the aforementioned case of write operation, the output signal xe2x80x9coutbxe2x80x9d of hvpp (3 V) that has xe2x80x9cHxe2x80x9d level is outputted when the input signal xe2x80x9cinxe2x80x9d at xe2x80x9cLxe2x80x9d level (reference voltage Vss of 0 V) is inputted, and the output signal xe2x80x9coutbxe2x80x9d is outputted at xe2x80x9cLxe2x80x9d level (Vss of 0 V) when the input signal xe2x80x9cinxe2x80x9d is inputted at xe2x80x9cHxe2x80x9d level (Vcc of 1.8 V).
However, the aforementioned conventional high voltage level shifter circuit provided with the cascade transistors, the operation of which is optimized (increased in size), has the following problems. FIG. 13 shows voltage waveforms in the high voltage level shifter circuit provided with the cascades for the column decoder that has the structure shown in FIG. 7 in the low voltage operation (power source hvpp=1.8 V). As is apparent from FIG. 13, a delay time (time from when the input signal xe2x80x9cinxe2x80x9d reaches the level of inversion to when the output signal xe2x80x9coutxe2x80x9d reaches the level of inversion) at the level of inversion during the transition from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level is 6.5 ns, meaning that the delay time is very large for one high voltage level shifter circuit. Moreover, the level of inversion is low in this case.
As described with reference to FIG. 8, the reason why the delay time is so long is ascribed to the operation optimization executed in the high voltage operation (power source hvpp=Vpp of 12 V), that is, increase to 104 xcexcm in the channel width of the n-MOS transistors Tr7 through Tr10. As described above in connection with the high voltage operation, when the operation at the high voltage is not optimized, that is, not increased in size, there is the possibility of occurrence of a trouble that the inverting operation might not be effected at the high voltage. Therefore, it is indispensable to optimize the operation at the high voltage, that is, to increase in size.
FIG. 14 shows voltage waveforms in the high voltage level shifter circuit that is not provided the cascade transistors shown in FIG. 6 in the low voltage operation (power source hvpp=1.8 V).
Also, in the high voltage level shifter circuit provided with the cascades for the row decoder having the structure shown in FIG. 12, the optimization of operation is executed in the high voltage operation (power source hvpp=Vpp of 12 V). Therefore, the level of inversion is lowered in the low voltage operation (power source hvpp=Vrc of 3 V), and the delay time at the level inversion when the output signal makes the transition from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level becomes disadvantageously long.
As described above, in the circuit construction of the flash memory shown in FIG. 11, there are long delay times in the operations of the high voltage level shifter circuits HV01, HV02, . . . and the high voltage level shifter circuits HV10, HV11, HV12, . . . during read i.e. in the low voltage operation. The above fact means that the timing of opening the select gate constructed of the transistors Tr01, Tr11, . . . is delayed by the high voltage level shifter circuits HV01, HV02, . . . when the input signal xe2x80x9cinxe2x80x9d is inputted sequentially to the high voltage level shifter circuits HV01, HV02, . . . on the column decoder side. The above fact also means that the rise of the word line W becomes late when the input signal xe2x80x9cinxe2x80x9d is inputted sequentially to the high voltage level shifter circuits HV10, HV11, HV12, . . . on the row decoder side. Consequently, there occurs the problem of the deterioration in access speed of the flash memory.
Accordingly, the object of the present invention is to provide a voltage level shifter circuit provided with an interposed cascade transistor capable of preventing an increase in delay time in the low voltage operation and a nonvolatile semiconductor storage device capable of preventing the deterioration in access speed.
In order to achieve the aforementioned object, according to a first aspect of the present invention, there is provided a voltage level shifter circuit, which converts an input signal whose high level is a power voltage of a device and whose low level is a reference voltage into an output signal whose high level is a first voltage and whose low level is a reference voltage, includes a cascade transistor for voltage alleviation and outputs at least two voltage levels of a first level and a second level as the first voltage according to a voltage level of a supplied power, the circuit comprising: a control voltage applying means for applying a second voltage to a gate of the cascade transistor in high voltage operation when a level of the first voltage becomes the first level higher than the power voltage, and for applying a third voltage to the gate of the cascade transistor in low voltage operation when the level of the first voltage becomes the second level equal to the power voltage.
According to the above-mentioned construction, it is assumed that, for example, a second voltage applied to the gate of the cascade transistor by the control voltage applying means is the power voltage in the high voltage operation. In the above case, the drain voltage of the transistor, which is turned on by the input signal and pulls in the potential of the output terminal from the first level higher than the power voltage to the reference voltage via the cascade transistor, becomes (power voltagexe2x88x92threshold voltage of cascade transistor) under the worst conditions. Therefore, the drain voltage does not exceed the gate voltage when the transistor is turned on, and the leak characteristic in the OFF state is not deteriorated.
On the other hand, it is assumed that, for example, a third voltage applied to the gate of the cascade transistor by the control voltage applying means is lower than the power voltage and not higher than the threshold voltage of the cascade transistor in the low voltage operation. In the above case, the current flowing through the cascade transistor is limited, and therefore, the pull-in speed of the transistor that pulls in the potential of the output terminal to the reference voltage is reduced. Therefore, even if the transistor for the pull-in use is momentarily turned on when the voltage of the output signal is inverted to the power voltage in response to the transition of the input signal, little influence is exerted on the inversion of the output signal to the power voltage, and the delay time of the level inversion of the output signal to the power voltage in response to the transition of the input signal is shortened.
In one embodiment of the first aspect of the present invention, the second voltage applied to the gate of the cascade transistor by the control voltage applying means in the high voltage operation is the power voltage preferably.
According to the above-mentioned construction, the drain voltage of the transistor, which is turned on by the input signal and pulls in the potential of the output terminal from the first level higher than the power voltage to the reference voltage via the cascade transistor, becomes (power voltagexe2x88x92threshold voltage of cascade transistor) under the worst conditions. Therefore, the drain voltage does not exceed the gate voltage when the transistor is turned on, and the leak characteristic in the OFF state is not deteriorated.
In one embodiment of the first aspect of the present invention, the third voltage applied to the gate of the cascade transistor by the control voltage applying means in the low voltage operation is lower than the power voltage and not lower than a threshold voltage of the cascade transistor preferably.
According to the above-mentioned construction, the current flowing through the cascade transistor is limited, and therefore, the pull-in speed of the transistor that pulls in the potential of the output terminal to the reference voltage is reduced. Therefore, even if the transistor for the pull-in use is momentarily turned on when the voltage of the output signal is inverted to the power voltage in response to the transition of the input signal, little influence is exerted on the inversion of the output signal to the power voltage, and the delay time of the level inversion of the output signal to the power voltage in response to the transition of the input signal is shortened.
In one embodiment of the first aspect of the present invention, the second voltage applied to the gate of the cascade transistor by the control voltage applying means in the high voltage operation is higher than the power voltage and is not higher than a voltage obtained by adding a threshold voltage of the cascade transistor to the power voltage preferably.
According to the above-mentioned construction, the second voltage applied to the gate of the cascade transistor in the high voltage operation is made higher than the power voltage. Therefore, the ability to flow a current when the cascade transistor is in the ON state is improved, and this allows the operation to be optimized even if the cascade transistor and the transistor that pulls in the potential of the output terminal via the cascade transistor are reduced in size.
In one embodiment of the first aspect of the present invention, the third voltage applied to the gate of the cascade transistor by the control voltage applying means in the low voltage operation is the power voltage preferably.
According to the above-mentioned construction, the ability to flow a current when the cascade transistor is in the ON state is reduced in the low voltage operation. Therefore, the level of inversion is shifted to the high voltage side for the aforementioned reasons, and the delay time of the level inversion of the output signal to the power voltage is shortened.
According to a second inventive aspect of the present invention, there is provided a voltage level shifter circuit, which converts an input signal whose high level is a fourth voltage and whose low level is a reference voltage into an output signal whose high level is a fifth voltage and whose low level is a reference voltage, includes a cascade transistor for voltage alleviation and a high voltage blocking transistor for the input signal and outputs at least two voltage levels of a third level and a fourth level as the fifth voltage according to a voltage level of a supplied power, the circuit comprising: a first control voltage applying means for applying a sixth voltage to a gate of the cascade transistor in high voltage operation when the fifth voltage level becomes the third level higher than the power voltage and applying an eighth voltage to the gate of the cascade transistor in low voltage operation when the fifth voltage level becomes the fourth level that is higher than the power voltage and lower than the third level; and a second control voltage applying means for applying a seventh voltage to the gate of the high voltage blocking transistor in the high voltage operation and applying a ninth voltage to the gate of the high voltage blocking transistor in the low voltage operation.
According to the above-mentioned construction, it is assumed that, for example, the sixth voltage applied to the gate of the cascade transistor by the first control voltage applying means in the high voltage operation is the power voltage. In the above case, the drain voltage of the transistor, which is turned on by the input signal and pulls in the potential of the output terminal from the third level higher than the power voltage to the reference voltage via the cascade transistor, becomes (power voltagexe2x88x92threshold voltage of cascade transistor) under the worst conditions. Therefore, the drain voltage does not exceed the gate voltage when the transistor is turned on, and the leak characteristic in the OFF state is not deteriorated.
On the other hand, it is assumed that, for example, the eighth voltage applied to the gate of the cascade transistor by the first the control voltage applying means in the low voltage operation is lower than the power voltage and not higher than the threshold voltage of the cascade transistor. In the above case, the current flowing through the cascade transistor is limited, and therefore, the pull-in speed of the transistor that pulls in the potential of the output terminal to the reference voltage is reduced. Therefore, even if the transistor for the pull-in use is momentarily turned on when the voltage of the output signal is inverted to the fifth voltage that has the fourth level in response to the transition of the input signal, little influence is exerted on the inversion of the output signal to the fifth voltage, and the delay time of the level inversion of the output signal to the fifth voltage in response to the transition of the input signal is shortened.
In one embodiment of the second aspect of the present invention, the sixth voltage applied to the gate of the cascade transistor by the first control voltage applying means and the seventh voltage applied to the gate of the high voltage blocking transistor by the second control voltage applying means in the high voltage operation are the power voltage preferably.
According to the above-mentioned construction, the drain voltage of the transistor, which is turned on by the input signal and pulls in the potential of the output terminal from the third level higher than the power voltage to the reference voltage via the cascade transistor, becomes (power voltagexe2x88x92threshold voltage of cascade transistor) under the worst conditions in the high voltage operation. Therefore, the drain voltage does not exceed the gate voltage when the transistor is turned on, and the leak characteristic in the OFF state is not deteriorated.
Furthermore, the power voltage is applied to the gate of the high voltage blocking transistor for the input signal. Therefore, normal operation can be achieved even if the fourth voltage, which is the high level voltage of the input signal, is a voltage higher than the power voltage.
In one embodiment of the second aspect of the present invention, the eighth voltage applied to the gate of the cascade transistor by the first control voltage applying means in the low voltage operation is lower than the power voltage and not lower than a threshold voltage of the cascade transistor, and the ninth voltage applied to the gate of the high voltage blocking transistor by the second control voltage applying means in the low voltage operation is lower than the power voltage and not lower than a threshold voltage of the high voltage blocking transistor, preferably.
According to the above-mentioned construction, the current flowing through the cascade transistor is limited in the low voltage operation, and therefore, the pull-in speed of the transistor that pulls in the potential of the output terminal to the reference voltage is reduced. Therefore, even if the transistor for the pull-in use is momentarily turned on when the voltage of the output signal is inverted to the fifth voltage in response to the transition of the input signal, little influence is exerted on the inversion of the output signal to the fifth voltage, and the delay time of the level inversion of the output signal to the fifth voltage in response to the transition of the input signal is shortened.
Furthermore, a voltage, which is lower than the power voltage and is not lower than the threshold voltage of the high voltage blocking transistor, is applied to the gate of the high voltage blocking transistor for the input signal. Therefore, normal operation can be achieved even if the fourth voltage, which is the high level voltage of the input signal, is a voltage higher than the power voltage.
In one embodiment of the second aspect of the present invention, the sixth voltage applied to the gate of the cascade transistor by the first control voltage applying means in the high voltage operation is higher than the power voltage and not higher than a voltage obtained by adding a threshold voltage of the cascade transistor to the power voltage, and the seventh voltage applied to the gate of the high voltage blocking transistor by the second control voltage applying means in the high voltage operation is higher than the power voltage and not higher than a voltage obtained by adding a threshold voltage of the high voltage blocking transistor to the power voltage, preferably.
According to the above-mentioned construction, the sixth voltage applied to the gate of the cascade transistor in the high voltage operation is made higher than the power voltage. Therefore, the ability to flow a urrent when the cascade transistor is in the ON state is improved, and this allows the operation to be optimized even if the cascade transistor and the transistor that pulls in the potential of the output terminal via the cascade transistor are reduced in size.
In one embodiment of the second aspect of the present invention, when the voltage applied to the gate of the cascade transistor in the high voltage operation is higher than the power voltage and not higher than a voltage obtained by adding a threshold voltage of the cascade transistor to the power voltage, the voltage applied to the gate of the cascade transistor by the first control voltage applying means in the low voltage operation are the power voltage, preferably.
According to the above-mentioned construction, the ability to flow a current when the cascade transistor is in the ON state is reduced in the low voltage operation. Therefore, the level of inversion is shifted to the high voltage side for the above-mentioned reasons, and the delay time of the level inversion of the output signal to the fifth voltage is shortened.
According to a third aspect of the present invention, there is provided a nonvolatile semiconductor storage device comprising a column decoder or a row decoder constructed of the voltage level shifter circuit as described in the embodiments of the present invention.
According to the above-mentioned construction, the voltage level shifter, which can prevent the deterioration in the leak characteristic in the OFF state and shorten the delay time of the inversion of the output signal to the high level, is employed for the column decoder or the row decoder. Therefore, the access time during read is shortened while preventing the current increase in the standby state in which no operation is executed and securing sufficient operation margins during write and read.